RT level test scheduling
Jan Blatný, Zdeněk Kotásek, Jan Hlavicka · 2002
The paper describes a new model of exploiting parallelism in testing of VLSI circuits. A circuit at the register transfer level is denoted as an RTL circuit. The model utilizes the concept of TACG (test application conflict graph). For the testing process the resource utilization model was defined and used for the TACG construction. The problem of concurrent test application is transformed to the one of TACG coloring and covering its nodes. Thus, the graph theory algorithms can be utilized for an RT level test scheduling. A methodology was defined that can be utilized during VLSI circuit design process, the final goal of which is to reduce the overall test application time of an RTL circuit.>