Making a real processor step by step using RISC-VISA
Jiangfang Yi, Cui Hongwei · 2018
The same as other courses, the Lab Course of Computer Architecture focuses on enhancing the understanding of basic concepts and theories. By completing our lab course, students can make a real processor step by step using RISC-V, an open source ISA of UC Berkeley. We have been designing and developing a microprocessor engineering pipeline and carefully designed different modules to develop the system capacity of our students. We design a set of new labs and use some flexible management strategies, such as Fuzzy C-Means algorithm, to guarantee the effectiveness of teaching. We applied them to Fall Semester in 2017. The feedback showed that the proposed goals had been achieved.