Exploration on Routing Configuration of HNoC with Reasonable Energy Consumption
Juan Fang, Zeqing Chang, Yanjin Cheng, Hui Zhao · 2018
The Heterogeneous Network-on-Chip (HNoC) integrates CPU cores, Graphic Processing Unit (GPU) cores, last-level-cache and memory controllers. The heterogeneity of this architecture inevitably brings resource contention and energy shortage. In this work, we evaluate the impact of different capacity of router buffers on communication delay and energy consumption. We run benchmarks to simulate different characteristics of the real-world applications, with the aim to balance performance with energy consumption under buffer resource limitations. Our evaluations of HNoC show that when the buffer resources are limited, by allocating more buffer to GPU, the energy consumption decrease by an average of 44.6%, while the performance degradation is negligible.