A Survey of Algorithmic and Architectural Modifications for Enhancing the Performance of Booth Multipliers
R. Nirmaladevi, R. Seshasayanan · 2018
Multiplication is the crucial operation in any DSP processor, since it requires more hardware resources and processing time. The performance of the multiplication is quantified with area, power and speed. Ever increasing demand for portable devices necessitates the design of high performance low power multipliers. Various high performance algorithms and architectures have been proposed in the design of multipliers. Number of partial products (PPs) has to be reduced to achieve low power dissipation. Booth algorithm is one of the most popular and fastest algorithm which reduces the number of partial product rows and there by the power dissipation. This paper is aimed to present a survey on booth multiplier. This survey will give researchers a brief idea about the algorithmic & architectural modifications in multipliers that are implemented in Booth algorithm so far.