A Study of 1+n/k Frequency Divider Based on Multi-Phase Clock
Mitsutoshi Yahara, Kuniaki Fujimoto, Hideo Kiyota · IEEJ Transactions on Electronics Information and Systems · 2018
In this paper, we propose the 1+n/k frequency divider based on the multi-phase clock. This circuit confirms that the desired dividing operation can be obtained under the condition ofn ≤ ⌊k/2⌋ by simulation. Also, since it is a full digital configuration, integration is easy.