Design of FPGA-based Mealy FSMs with Counters
Alexander A. Barkalov, Larysa Titarenko, Kamil Mielcarek, Sławomir Chmielewski · 2018
A method is proposed for hardware reduction of FPGA-based Mealy FSM's logic circuit. The method is based on replacement of state register by state counter. The content of the counter can be increased during both conditional and unconditional transitions. There is an example of application of proposed method.