Study and Implementation of Optimized Solutions for Re-Configurable Logic over ASIC Design Flow
Araújo, Ricardo Azevedo · Open Repository of the University of Porto (University of Porto) · 2018
The intent of this thesis ,as proposed by Synopsys, is to develop a process by which specific circuits of an ASIC design are replaced by reconfigurable logic using a limited sub-set of technology standard cells. The usage will be targeted to control logic, which has typically lower frequency requirements. The work shall focus on a flow that minimizes the involvement of the ASIC RTL designer and comply with the verification needs concerning name mapping between original RTL and produced circuit. During the development of the new flow other works on the subject, such as the one done in the previous thesis "Automatic implementation of a re-configurable logic over ASIC design flow" also developed at Synopsys, will be considered and solutions already developed but unsuccessfully will be ruled out.