Carrier-Scale Packet Processing System Using Interleaved 3D-Stacked DRAM
Tomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki · 2018
Emergence of new network services such as Internet of Things (IoT) and edge computing accelerates the increase of traffic volume, the number of connected devices and the diversity of communication. Next generation carrier network infrastructure should be much more scalable and adaptive to rapid increase and divergence of network demand with much lower cost. More virtualization-aware, flexible and inexpensive system based on general-purpose hardware is necessary to transform traditional carrier network into more adaptive, next generation network. In this paper, we propose a carrier-scale packet processing system which utilizes 3 Dimensional (3D)-stacked Dynamic Random Access Memory (DRAM) device. The proposed system augments memory access concurrency by leveraging vault-level parallelism and bank interleaving of 3D-stacked DRAM. The system uses hash-function-based distributor of memory requests to each set of vault and bank which accommodates a portion of original carrier-scale huge tables. We introduce an analytical model for the system. The evaluation result shows that our proposed system can achieve more than 100 Gbps in carrier-scale packet processing where main memory accesses are inevitable since tiny CPU cache memory is insufficient to accommodate huge tables. Our analytical model is independent of specification of a particular device, which can be applied to any DRAM systems.