Towards Embedded Systems Formal Verification Translation from SysML into Petri Nets
Wojciech Szmuc, Tomasz Szmuc · 2018
A verification of embedded systems described using SysML is considered. The main idea consists in translation of SysML artifacts into Colored Petri Net models. The paper focuses on mapping of main building units, the so-called blocks into the corresponding nets. The nets may be verified directly or using Temporal Logic provers.