Evaluation of MD5Hash Kernel on OpenCL FPGA Platform
Zheming Jin, Hal Finkel · 2018
Field-Programmable Gate Array (FPGA) is a promising choice as a heterogeneous computing component for energy-aware high-performance computing applications. The emerging high-level synthesis (HLS) tools such as Intel OpenCL SDK provide a streamlined design flow to facilitate the use of FPGAs. In this paper, we are focused on the evaluation of the MD5 hashing kernel in the scalable heterogeneous computing (SHOC) bench suite. We explain the kernel and then evaluate the resource usage, performance, and performance per watt of the kernel implementations on the FPGA. The experimental results show that the optimized implementation using kernel duplication can achieve a factor of 6.1 X speedup over the naïve code on the Nallatech 385A FPGA card that features an Arria 10 FPGA chip. For the performance per watt, we achieve 43 million hashes per watt on an Intel Arria 10 GX1150 FPGA, which is 39.7X, 15.6X, and 1.07X improvement over a dual-socket Intel Xeon E5-2687W processor, an Intel Xeon Phi Knights Landing 7210 processor, and an Nvidia K80 GPU, respectively.