IMPLEMENTATION OF LOW POWER DELAY PULSED LATCHES FOR SHIFT REGISTER USING KOGGE STONE ADDER
B Ashok, Thulimilli Prem Bosco · IJITR International Journal of Innovative Technology and Research - IJITR International Journal of Innovative Technology and Research · 2017
This project proposes delay efficient architecture for shift registers using pulsed latches instead of filp flops. Area and power can be reduced greatly by using latches then flip flops. The timing problem exhibited by the latches is reduced by taking necessary delays in pulses for latches. This includes a counter for generating pulses with delays. For obtaining these delays counter has to incremented by 1. The proposed kogge stone architecture reduces the delay to maximum extent, and produces numerious variation between conventional adder architecture.