The Raw Compiler Project
Anant K. Agarwal, Saman P. Amarasinghe, Rajeev K. Barua, Matthew I. Frank, W. Lee, Vivek Sarkar, Devabhaktuni Srikrishna, Michael Bedford Taylor · 1999
Compilers today are capable of inferring detailed informationabout program parallelism and analyzing whole-program behavior. However, the traditionalinterface between the compiler and the processor, as defined by the instruction set architecture (ISA), is unable to communicate much of the compiler knowledge to the processor. The approach taken by modern processors such as superscalars is to incorporate purely run-time algorithms in their hardware to perform analyses and optimizations such as detection of instruction-level parallelism. However, these complex hardware implementations can only exploit a small fraction of the parallelism information available to the compiler. The Raw architecture developed at MIT aims to maximally utilize the compiler by fully exposing the hardware and by delegating the hardware’s control completely to the software system. The Raw microprocessor, a set of simple RISC-like processor tiles interconnected with a high-speed 2D mesh network, does not provide hardware implementations for any of the complex algorithms found in conventional microprocessors. Instead, the compiler and the run-time software system fully orchestrate the Raw hardware resources, and they implement run-time analyses and optimizations tailored to the need of each individual application. This novel approach provides many opportunities and challenges for the Raw compiler and run-time system. 1 1