QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications
Serhiy Avramenko, Siavoosh Payandeh Azad, Stefano Esposito, Behrad Niazmand, Massimo Violante, Jaan Raik, Maksim Jenihhin · 2018
Multi-Processor Systems-on-Chip (MPSoCs) have been a clear new trend in processor-based systems design. General purpose MPSoC designers have turned to the Network-on-Chip (NoC) interconnect model to surpass the limitations imposed by traditional bus- or crossbar-based interconnection. This technology is also a promising solution for safety-critical industries where, primarily due to power and weight constraints, there is an increasing need in embedded systems for implementing multiple functionalities upon a single shared computing platform. This paper proposes a QoSinNoC framework, which is based on a set of quality of service (QoS) aware NoC architectures along with the analysis methodology including selected relevant metrics that enable an efficient trade-off between guarantees and overheads in mixed-criticality application scenarios. QoSinNoC architectures overcome the notion of strictly divided regions by allowing non-critical communication pass through the critical region, providing they do not utilize common router resources. This work aims to facilitate the usage of NoC technology by safety-critical industries such as avionics.