Hardware Optimizations and Analysis for the WG-16 Cipher with Tower Field Arithmetic
Nuša Zidarič, Mark D. Aagaard, Guang Gong · IEEE Transactions on Computers · 2018
This paper explores tower field constructions and hardware optimizations for the WG-16 stream cipher. The constructions${\mathbb {F}}_{(((2^2)^2)^2)^2}$and${\mathbb {F}}_{(2^{4})^4}$were chosen because their small subfields enable high speed arithmetic implementations and their regularity provides flexibility in pipeline granularity. A design methodology is presented where the tower field constructions guide how to proceed systematically from algebraic optimizations, through initial hardware implementation, selection of submodules, pipelining, and finally detailed hardware optimizations to increase clock speed. The highest frequency WG(16, 32) keystream generator, obtained for the 65 nm ASIC library, reached a clock speed of 2.44 GHz at 26.3 kGE, and the smallest area keystream generator achieved a clock speed of 0.33 GHz at 9.9 kGE. The highest frequency FPGA implementation on a Xilinx Spartan 6 reached a clock speed of 256 MHz using 631 slices. In addition, the paper demonstrates that LFSR feedback polynomials can be optimized to increase security without hurting performance, and retiming optimizations can be used to increase clock speed without increasing area.