Delay Efficient 128-Bit Ladner-Fischer Adder
B. Tapasvi et al., B. Tapasvi et al.,, TJPRC · International journal of electronics, communication & instrumentation engineering research and development/International journal of electronics, communiction & instrumentation engineering research and development · 2018
This paper describes the VLSI Architecture for High-Speed 128-bit Ladner-Fischer adder.The performance of Ladner-Fischer adder with black cell takes huge memory.So, the gray cell can be replaced instead of black cell that improves the Efficiency in Ladner-Fischer Adder.The three stages of operations include pre-processing stage, carry generation stage, post-processing stage.In ripple carry, adder each bit of addition need to wait for the previous bit carry.In efficient Ladner -Fischer adder, addition operation does not wait for previous bit carry since ripple carry adders are replaced by Carry select Adder (CSLA) and Binary to Excess-1 code Converter (BEC) to improve the speed and to decrease the memory used.