FPGA implementation of vertical addition with a bitwise pipeline of calculations
Julia V. Drozd, Oleksandr Drozd, Valeria Nikul, Julian Sulima · 2018 IEEE 9th International Conference on Dependable Systems, Services and Technologies (DESSERT) · 2018
Design of arithmetical nodes faced at the beginning of the way a choice between horizontal and vertical data processing, the matrix and pipeline circuit decisions. A choice was made in favor of the horizontal processing of numbers with the use of the array structures. This paper analyzes logic of the choice and further perspective of the specified opposition. Vertical data processing and the bitwise pipelining of operations have a row of advantages in the multi-operand calculations and in supporting of a checkability of the digital circuits. However, long-term information technology development significantly strengthened line items of the selected way by an experience of the arithmetical nodes design, including the modern CAD. They are oriented on an execution of the horizontal operations on array structures and contain big libraries of the ready decisions. That's why the research of circuits with the vertical data processing on the basis of the bitwise pipelining of calculations attracts interest regarding a success of their implementation in FPGA projects. The pilot studies are conducted with the use of a CAD of Intel Altera Quartus II on the example of circuit decisions in vertical addition of a set of numbers with the bitwise pipelines. The comparative analysis of the received circuits with library decisions is made on indices of their complexity, throughput and energy consumption.