Design of a Low Power Vedic Multiplier using BKG Reversible Logic Gate
S M Mayur · International Journal for Research in Applied Science and Engineering Technology · 2018
This work shows the architecture of low power digital circuits implemented using BKG reversible logic gate.In digital circuits power dissipation can be significantly reduced using reversible logic.It is becoming prominent in applications involving quantum computing and low power applications.BKG is a 4x4 reversible logic gate i.e, it has 4 inputs and 4 outputs out of which 1 input is a ancilla input and 2 out of 4 outputs are garbage outputs.The outputs can be uniquely retrieved from the inputs and vice versa.BKG half adder shows 84.17% reduction in the power consumption when compared to half adder implemented using Feynman and Fredkin reversible gate.It also shows a 79.59% and 25.66% reduction in the power consumption when compared to half adder implemented using MIG and COG reversible gate and Peres reversible logic gate respectively.Since BKG is proved to be better than all the existing reversible logic gates, it is used to implement applications such as encoders and various multipliers.