Low-capture-power X-filling method based on architecture using selection expansion
Yu-Ting Chung, Jiann-Chyi Rau · 2018 IEEE International Conference on Applied System Invention (ICASI) · 2018
In the system-on-chip(SOC) design, there are a huge volume of test data. The arrival of test data compression is because of lacking in channel capacity and the restricted memory of Automatic Test Equipment (ATE). Therefore, the technique of test data compression is very important to save time and memory. Because of MISR's characteristic, we can use one ATE data to run lots of times. In this paper we use selection with Flip-Flops to spread MISR data. Each Flip-Flop of MISR is connecting with 2 MUXs of selection. And selection connected with MISR. To use Flip-Flops so we can restore bits in it, just changing Flip-Flops bits when data changing. It is not frequently changing of the bits of Flip-Flops, so we can decrease power consumption. In our architecture we already saved some shift power. In this paper we will approach a Low-Capture-Power X-Filling Method to decrease shift times of Flip-Flops. Compare to Random X-filling Method, the FC will be the same but less average and maximum shift times.