A Security-Aware Pre-partitioning Technique for 3D Integrated Circuits
Siroos Madani, Magdy Bayoumi · 2017
Outsourcing the chip for fabrication is an efficient way to save money and reduce time to market. However, it raises numerous security challenges for chip designers, as some of the foundries try to identify the functionality of the chip to take its ownership. Furthermore, some foundries may insert a Trojan circuit to affect the functionality of the chip or steal valuable information about the design such as encryption key. Each Trojan may utilize low toggle (LT) nets to trigger its activation [1]. Hence, it is tough to detect a Trojan circuit during the testing step as it lies dormant for ages and waits until its rare activation conditions are met. Consequently, some mechanisms are required to neutralize the attacker's plans for inserting a Trojan circuit. 3D Integrated circuit (3D-IC) can be a practical solution to the challenges that threaten the security of the chip. One of the famous features of 3D-IC is its capability of split manufacturing of the chip, as the whole design can be distributed among different tiers in the 3D stack. Tiers containing critical logic blocks are sent to a trusted local foundry to be fabricated while the less significant tiers are sent to the less reliable foundries to save money. In this work, we propose a method to sabotage the trigger criteria for a hardware Trojan. To do so we obscure root LT nets by replacing each of them with a vertical interconnect known as Through Silicon Via (TSV) in a 3D-IC structure. A root (earliest ancestor) LT net is defined as a net that is the origin of other LT nets. As we will discuss in section IV, obscuring a root LT net will result in hiding the toggle characteristics of its offspring LT nets. Therefore, untrusted foundries will not be able to exploit LT nets for activating their Trojan circuits. They may even use the high toggle nets for enabling the Trojan circuit. Thus, the chance of Trojan circuit getting compromised during the testing process will be high. In the end, list of root LT nets obtained from our algorithm will be used in upcoming partitioning stage to boost the security of the design.