Error Characterization and ECC Usage Relaxation beyond 20nm Floating Gate NAND Flash Memory
S.H. Ku, T.W. Lin, C.H. Cheng, C. W. Lee, Ti-Wen Chen, Wen-Jer Tsai, T.C. Lu, W.P. Lu, K.C. Chen, Tahui Wang, Chih-Yuan Lu · 2018
Endurance of floating gate flash memories at 19nm node and beyond is studied comprehensively. Experiments reveal that the random telegraph noise (RTN) would degrade the read margin with a tail, which quickly reshapes into a symmetric Gaussian form in a lightly-stressed state. After heavy stress, the lower part of tail would spread further while the upper part keeps roughly overlapped with that during fresh. This unique behavior, which was firstly measured by the self-established Budget Product Tester (BPT), can be explained by stress-induced hole trap creation. To investigate the impact of RTN on operation window, a novel algorithm of Multi-Times-Verify accompanied with the optimal Read-Retry (MTVR2) is proposed and validated by BPT. The advantage of MTVR2to reduce the requirement of Error-Correcting Code (ECC) bit is demonstrated. Finally, the improvement of bit error rate (BER) in TLC operation with MTVR2is also evaluated.