A modular digital VLSI flow for high-productivity SoC design
Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons, Joel Emer, Matthew R. Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Pinckney, Yakun Sophia Shao, S Srinath, Christopher Torng, Sam Likun Xi, Yanqing Zhang, Brian Zimmer · 2018
A high-productivity digital VLSI flow for designing complex SoCs is presented. The flow includes high-level synthesis tools, an object-oriented library of synthesizable SystemC and C++ components, and a modular VLSI physical design approach based on fine-grained globally asynchronous locally synchronous (GALS) clocking. The flow was demonstrated on a 16nm FinFET testchip targeting machine learning and computer vision.