Hybrid Model of 64- Bit Adders and Subtractors
M. Hariesh Kumar · International Journal for Research in Applied Science and Engineering Technology · 2018
The increasing demand of large memory devices and electronics circuit with small area and high speed of processing increase the popularity of these device .For large memory devices there will be higher bit addition subtraction like 64-bit addition\subtraction and 128 -bit addition subtraction.This paper include the designed model of 64-bit adder , subtractor, hybrid adder and the compression of their different parameters by using Xillinx 8.2 software.CMOS logic, transmission gate logic and pass transistor logic are used Keywords: Ripple Carry Adder (RCA),Carry Look ahead Adder (CLA), Ripple Borrow Adder (RBA), Input Output Bounded (IOB), Select Line (SL).I.