Efficiency evaluation of a SystemVerilog-based real number model
Nikolaos Georgoulopoulos, Alkis A. Hatzopoulos · 2018
Real Number Modeling (RNM) is the process of modeling an analog circuit's behavior as signal flow model. This means that every output of an analog component is sampled, in a discrete manner, from the inputs and the internal state. The model detects an event and decides the time to carry out a computation. A SystemVerilog behavioral real number model for a comparator is presented, in order to improve simulation efficiency. The comparator model simulation time completes in only 154ms, which can be utilized effectively in high-speed analog-to-digital converters (ADCs). The proposed model is compared to three different models: a transistor-level CMOS comparator, a Verilog-A and a Verilog-AMS with wreal models. 65nm CMOS technology library was used for the comparator designs in Cadence Virtuoso. The simulation runs took place in Spectre (for transistor-level SPICE model) and AMS Simulator (for System Verilog, Verilog-A and Verilog-AMS with wreal). In all cases, the presented SystemVerilog model displays high gains in simulation run time, along with satisfying accuracy.