Data representation and hardware aspects in a fully-folded successive-cancellation polar decoder
Chris Andriakopoulos, Vassilis Paliouras · 2018
In this paper, we introduce a hardware architecture for a polar-code decoder based on Successive Cancellation (SC). SC, proposed by Arikan, achieves the capacity of binary erasure channel. We propose an architecture for a fully-folded SC decoder, of which the basic component is a butterfly. This butterfly performs all computations on the SC data flow graph, while LLRs and partial results are stored in RAMs. Furthermore the impact of LLR quantization and internal data representation on BER performance is studied for codes with block-length of 512, 1024 and 2048 bits. A data representation scheme is proposed and it is shown to lead to 30-50% reduction of required memory, for practical block lengths. The reduction achieved increases with block length.