VLSI Design of a Novel Architecture for Data Encoding with Golay codes
E. Odevi · International Journal for Research in Applied Science and Engineering Technology · 2018
There is an expanding interest for productive and dependable transmission of computerized information. A noteworthy worry here is the control of blunders for dependable generation of information. By appropriate encoding of data to a codeword with the assistance of Error Correction Codes (ECC), errors induced can be reduced. The proposed architecture parallelizes the comparison of the data and that of the parity information. To further reduce the latency and complexity, in addition, a new butterfly-formed weight accumulator (BWA) is proposed for the proficient calculation of the Hamming separation. Grounded on the BWA, the proposed design analyzes whether the approaching information coordinates the put away information if a specific number of wrong bits are amended. . The proposed engineering is actualized by utilizing xilinx14.7 form and the trial comes about demonstrate that the proposed design lessens the dormancy and the equipment multifaceted nature separately. In expansion we do Golay code for more decrease in the idleness. Golay code is a different mistake adjusting parallel code equipped for remedying a blend of three or couple of arbitrary blunders in a piece of 23 digits. The Comparison of Golay Code and BWA is due to Delay and Speed.