Fault-Driven Reconfiguration Algorithm for Processor Arrays
Yalan Wu, Jigang Wu, Yuqing Miu, Thambipillai Srikanthan · 2017
With the development of VLSI technology, the reliability of multi-processor systems on a single chip increases, such that the processor array can work with very small faults. This paper proposes a fast and very efficient reconfiguration algorithm for the processor arrays with small faults which frequently occurs in real-time systems. So far, most existing reconfiguration algorithms always traverse all available processors to construct a logical array. Motivated by that the number of the faulty processors is generally very small, the proposed algorithm, named FDA in this paper, focuses on the faulty processors and their locations, instead of available processors as the traditional approaches did. The algorithm FDA shifts as much faulty processors as possible to the same logical columns, in order to keep the available links used in the target array. Simulation results show that, for the random faults, the proposed FDA is fast and very efficient for the case of small faults. On 128×128 physical arrays with fault density less than 0.01%, it can achieve significant acceleration, without loss of logical columns. For the fault density less than 1%, the algorithm FDA successfully accelerates reconfiguration of the logical arrays by 74.38% on average, while the number of logical columns decreases at most 4.07%. Especially for the case of central clustered faults, FDA successfully accelerates reconfiguration by 98.41% on average, although the number of logical columns decreases at most 4.35%.