A Compression Instruction Set Design based on RISC-V for Network Packet Forwarding
Z Cao, Q Lv, Y Wang, Mei Wen, N Wu, Chao Zhang · Journal of Physics Conference Series · 2018
The multi-core processor of RISC for network packet forwarding has been limited by the on-chip storage space. As more and more cores are implemented in one chip, the storage resources allocated by each core on the chip become less and less, as well as the conflict of visiting RAM has become more prominent. Therefore, the use of more compact instruction size will reduce the number of visits, and get a higher instruction cache hit rate, thereby improving the performance of the application and energy efficiency. Based on the open source instruction set RISC-V, this paper proposes a compressed ISA for the network packet forwarding. It is proved by experiment that the new instruction set which customized by this method has higher compression efficiency and better system performance for the network packet forwarding applications.