Design automation methodology of a critical path monitor for adaptive voltage controls
Ryosuke Kazami, Hayate Okuhara, Hideharu Amano · 2018
The development of recent CMOS technologies such as Fully Depleted Silicon on Insulator (FD-SOI) allows VLSI systems to operate with lower power than the conventional bulk transistors [1, 2]. Thanks to its high degree of noise immunity, low power supply voltages (VDD) can be applied to the FD-SOI devices. Also, since the effect of body biasing is further endorsed in such devices, adaptive voltage control for both power supply voltage and body bias voltages (VBNfor nMOS and VBPfor pMOS) can be aggressively used.