A pipeline ROM-less DDFS using equal-division interpolation
Tsung-Yi Tsai, Hsiang-Yu Shih, Chua‐Chin Wang · 2017
A pipeline ROM-less direct digital frequency synthesizer (DDFS) with equal division interpolation is proposed in this investigation. In order to get higher SFDR and faster clock rate, different segments with various interpolation equations are analyzed. 2nd-order parabolic equations with proper selection of coefficients based on hardware cost is utilized to transcend the limitation of SFDR. Thus, a 4-stage pipeline architecture is realized to achieve better clock speed. This work demonstrates the maximum SFDR for 102 dBc and the output frequency for 50 MHz using TSMC 0.18μm CMOS technology cell library.