Impolite High Speed Interfaces with Asynchronous Pulse Logic
Merritt P. Miller, Carrie Segal, David Mc Carthy, Aditya Dalakoti, Prashansa Mukim, Forrest D. Brewer · 2018
We present a design solution that allows design of higher-than-core rate operation with techniques that avoid PLL/DLL blocks to provide higher speed timing. Many modern integrated circuits (ICs) have high speed interfaces which operate at higher cycle rates than the core of the IC. As a result of the higher-than-core rate, these interfaces are not directly representable in the core sequential logic. Asynchronous pulse logic offers an alternative design method for high speed interfaces with similar performance, simpler circuitry and without resorting to high-power logic cells such as emitter coupled logic. Formal and practical considerations for constructing high-speed interfaces are described. Gate designs and timing information for example cases are presented. These cases suggest that 80% improvements on rate compared traditional clocked logic are possible.