Design of 32-bits RISC processor for hardware efficient QR decomposition
Safaa S. Omran, Ahmed K. Abdul-abbas · 2018
The QR decomposition (QRD) is an implementation prerequisite for many different detection algorithms in MIMO (multiple-input multiple-output) wisely communication system. In this paper, a QR decomposition core processor which decomposes a matrix into an orthogonal and triangular matrix using Gram-Schmidt orthonormalization method is designed and implemented using a 32-bit RISC processor based on FPGA.