LARECD: Low area overhead and reliable error correction DMR architecture
Hyunyul Lim, Tae-Hyun Kim, Dongsu Lee, Sungho Kang · 2017
Recent HPC system generally is composed of enormous amounts of GPUs. GPU-based HPC system makes a reliability problem from the absence of error detection unit in GPUs. For improving the reliability of GPU, dual modular redundancy(DMR) architecture is presented. However, current DMR architectures do not care much to the correction sequence. Therefore, the data hazard can occur during the recovery sequence. We present LARECD (Low Area overhead and Reliable Error Correction DMR) architecture. This architecture can secure the error correction sequence from the data hazard. Experimental result demonstrates the efficiency of LARECD architecture.