Efficient Mapping of a 64 Point Pipelined Architecture
Merlin Ponnachan · International Journal for Research in Applied Science and Engineering Technology · 2018
In this paper, a pipelined Single-Path Delay Feedback (SDF) Fast Fourier Transform (FFT) architecture is efficiently mapped to Field-Programmable Gate Arrays (FPGAs). Several Algorithmic transformations are proposed that allow a better mapping of the architecture. To get better implementation results, target FPGAs architectural features are considered. A R2 2 SDF FFT core for 64-point is mapped to Xilinx Virtex-6 device. The resulting Virtex-6 design gives an increase in throughput per slice, uses half as many DSP blocks. The architecture is simulated on Xilinx ISE 14.2 ISim with Speed grade -2 and at a maximum frequency of 167.259MHz.