LEIA: A 2.05mm2 140mW lattice encryption instruction accelerator in 40nm CMOS
Shiming Song, Wei Tang, Thomas Chen, Zhengya Zhang · 2018
The recent rapid steps towards commercialization of quantum computing services have been calling for the deployment of post-quantum (PQ) security schemes at a large scale. This work presents a high-performance, programmable lattice encryption instruction accelerator named LEIA that supports all the recent popular ring learning with errors (ring-LWE) schemes, with parameter N from 64 to 2048, and q from 2 to 232-1. LEIA is prototyped in a 2.05mm240nm CMOS test chip. It achieves significant speedup and energy efficiency in core operations required by ring-LWE: above 1000× acceleration and 2000× better energy efficiency in number theoretic transform (NTT), and above 10× acceleration and 50× better energy efficiency in high-σ, high-precision discrete Gaussian (DG) generation over state-of-the-art designs using the most challenging published parameter settings. As the first silicon-proven lattice encryption accelerator, LEIA is the fastest, most energy-efficient, and most configurable solution to date.