Implementation of a Cache-Based IPv6 Lookup System with Hashing
Bachir Fradj, Benjamin Wolff, Normand Bélanger, Yvon Savaria · 2018
Due to the rapid growth of traffic on the Internet, the IP lookup process imposes ever-growing performance requirements in order to avoid that it becomes a bottleneck during packet forwarding. This complex function is often implemented by hardware accelerators that are integrated with a processor. In this paper, we use a modified cache memory as an accelerator to perform IP lookup. Hashing is used for mapping each bucket of a hash table to a set of the cache memory. We show that, in the proposed scheme, a table of 26K prefixes fits into a cache of 1MB and the throughput achieved allows processing packets at wire speed over four 40Gb links.