A High Constancy Rail-to-rail Level Shift Generator for SEIR-based BIST circuit for ADCs
Hao Meng, R.L. Geiger, Degang J. Chen · 2018
Built-in self-test(BIST) for AMS circuit is widely investigated and developed in the last decade since it is a promising alternative to traditional testing. In particular, SEIR (stimulus error identification and removal) based BIST circuit has been proved to be a cost effective and practical ADC BIST solution for ADC testing. The SEIR method can relax the linearity requirement of input signal for ADC. However, high constancy of level shift between two signals are needed for testing high resolution ADC's linearity. This paper presents a new method to introduce the highly constant level shift and a new structure of output buffer with true rail-to-rail performance without degrading close-loop gain by applying correlated level shifting (CLS)technique. The simulation results show that the constancy of level shift is only 2.2ppm over the entire ADC input range. The constancy level is able to test 18 bit ADC to 18 bit accuracy level for full-codes testing.