Prioritized Pwdedf Scheduling Algorithm For Qos Enhancement Using Network Processor
Anna · i-manager s Journal on Communication Engineering and Systems · 2014
Multimedia traffic is becoming an increasing portion of today's Internet traffic due to the multimedia applications such as music/video streaming, IP telephony, video teleconferencing, and distance learning. These wide range of communication-intensive, real-time multimedia applications require timing and other QoS features (Throughput, End to end delay, Delay variation (jitter), Error rate, Multicasting and broadcasting capabilities). It puts more burden on the routers and requires the next generation IP routers to be QoS-capable . Providing quality of service (QoS) guarantees in packet network requires the use of traffic scheduling algorithms in the routers. The aim of a scheduling algorithm is to determine the order in which packets of various independent flows are to be forwarded over the output link.FIFO (First-In-First-Out) scheduling, perhaps the simplest to implement, does not provide any isolation between individual sessions which is necessary to achieve deterministic bandwidth guarantees. The basic idea of an IP router is to route packets. However, a QoS-capable IP router should have the following functionalities such as receiving IP packets from incoming links, IP header analysis (such as packet classification, QoS analysis), Routing table lookup, QoS -aware packet scheduling, and Transmitting packets to outgoing links. By All these functionalities must be parallelized in order to make the router a high performance one. Traditional router is mainly based on general-purpose CPU and fixedfunction Application Specific Integrated Circuits (ASICs) technology. In software-based routers built on CPU, all the packet-processing functions are implemented in software running on general purpose processors. Though new features could be added simply by upgrading the system software, such flexibility is accompanied with limited ability to support higher bandwidth and additional features. ASICs can provide maximum performance, but provides little flexibility when the type or nature of the media interfaces change or new protocol standards require changes, because once all the instructions or logic are embedded in silicon, it is difficult to change them to add new features. Therefore, router with a network processor can be a solution to develop QoS capable router. Processors (NPs) that can be placed in the routers to execute various tasks in the network. These tasks can range from IP table lookup algorithm to application level multimedia transcoding applications. The network processor consists of a number of on chip processors to carry out the packet level parallel processing operations. It provides a set of instructions optimized for packet processing, as well as a set of hierarchically distributed