Parallel Prefix Adder Using Static Conventional Logic Gates
D. Divya · i-manager s Journal on Circuits and Systems · 2015
As we know, synchronous circuits have many disadvantages like the clock skew problem, sensitive to variation in physical parameters, no module reusability, and more power consumption [1] . These disadvantages are overcome by asynchronous circuits and mainly the clock skew problem is eliminated because, they are clock-less devices. In asynchronous circuits, event sequencing and control depends on local handshake protocols rather than on a global clock signal [2] . Here, quasi-delay insensitive (QDI) circuits are used; these circuits are correct-by-construction that uses multi-rail signals. It gives an average case performance rather than a worse case performance [3] . Quasi-delay circuits are glitch free circuits and can be easily interfaced with multi-rated circuits. An adder plays a vital role in digital signal processing systems. Parallel Prefix Adder is a high speed adder with regular fan-out. The main objective of parallel prefix adder using static conventional logic gates is to reduce the power consumption, delay and to increase the speed. Though the area overhead problem occurs by using static NCL By gates, power consumption can be reduced by simply disconnecting the power rail between the gate terminal and the supply voltage. Asynchronous techniques such as, Null Convention Logic (NCL) have many advantages due to the elimination of global clock and here the timing analysis is not necessary for the correct operation. Dual-rail signal encoding is more popular, and it is similar to the traditional boolean logic. Assuming isochronic wire forks [6], they must meet the input-completeness and observability criteria [4] . Table 1 shows the dual-rail signal encoding. A dual rail signal, D, 0 1 0 consists of two wires, D and D . If D is one, then only DATA0 1 0 will assert. If D is one, then only DATA1 will assert. If both D 1 0 1 and D are zero then NULL is asserted. If both D and D are one, then it is coded as INVALID [5]. Using the dual rail