VLSI Architecture of High Speed SAD for High Efficiency Video Coding (HEVC) Encoder
Amit M. Joshi, Mohd. Samar Ansari, Chitrakant Sahu · 2018
This paper presents the architecture of integer motion estimation for HEVC encoder. Our proposed architecture uses pipelined design with parallel processing to increase the performance and reduce computation time. The architecture has 16 processing unit to calculate sum of absolute difference (SAD) of all possible blocks from 4×4 to 64×64. The architecture has flexibility to adapt any kind of search algorithms including full and fast search. This architecture is prototyped and simulated on Xilinx Virtex-5 FPGA for XC5VLX20T family. Our architecture works on 65 nm technology and attains a maximum clock frequency of 475.21 MHz. The performance of algorithm is compared and has better speed than similar works.