Optimized BIST architecture for memory cores and logic circuits using CLFSR
Preethy K John, P Rony Antony · 2017
Built-In Self-Test is a design for testability method for testing embedded circuits. It provides simple automated test procedures to detect faults in Memory Cores and logic circuits in a system. This paper describes a model of BIST structure that can be used as Memory BIST or Logic BIST. For testing a logic circuit we need test vectors. In the case of memory testing, addressing sequences in addition to the test vectors are required. In this paper an alternative method is used for the generation of both address and test data with less hardware complexity. This is achieved by modifying Linear Feedback Shift Register to a structure known as Complete Linear Feedback Shift Register (CLFSR). With CLFSR, all possible combinations of ones and zeros can be generated. This feature enables it for using in Memory BIST and Logic BIST structures. Hence, a CLFSR structure can be used to develop less complex BIST architecture. Functionality of CLFSR and BIST structures are verified using Xilinx ISE 14.2.