A Study of a Fault-Tolerant System Using Dynamic Partial Reconfiguration
Seiya Ogido, Chikatoshi Yamada, Kei Miyagi, Shûichi Ichikawa · 2017
In this paper, we propose reconfigurable fault tolerant architecture which can recovery from failure status with spare space. Generally, embedded processors are required to need high reliability. In particular, tile structure which is the key of the architecture for the reconfigurable device. We propose reconstruction for circuits by using the Tcl script. The proposed method is kept the reliability by redundant of circuit. We discuss trade-off for implementation using Xilinx FPGAs.