FPGA-based packets processing acceleration platform for VNF
Tianyi Lan, Qing Tian Han, Hongwei Fan, Julong Lan · 2017
While there has been a belief over the past few years that virtual network functions (VNFs) should be built on common servers, we argue that it can lead to limited performance and large up/down traffic. This paper proposes a new idea of shifting part of NFV functions from software packages to common hardware devices to promote overall performance. Then we present the design and implementation of PPAP, a Packets Processing Acceleration Platform for NFV. It offers high flexibility by allowing functions to control the processing flow of hardware. Dynamic match tables and virtualization techniques ensure isolation among VNF instances.