An efficient implementation of SHA processor including three hash algorithms (SHA-512, SHA-512/224, SHA-512/256)
Sang-Hyun Lee, Kyung-Wook Shin · 2018 International Conference on Electronics, Information, and Communication (ICEIC) · 2018
This paper describes a design of SHA processor implementing three hash algorithms of SHA-512, SHA-512/224 and SHA-512/256. The SHA processor generates digests of three different lengths with 512, 224, and 256 bits according to hash algorithms. It was designed that the initial hash values of SHA-512/224 and SHA-512/256 were generated using SHA-512 and it was based on 32-bit datapath, resulting in an area-efficient implementation. The SHA processor designed with HDL was verified by FPGA implementation. The SHA processor synthesized with 0.18ßm CMOS cell library occupies 27,368 gate equivalents (GEs) and can operate up to 185 MHz clock frequency. The SHA processor can be used for IoT security applications.