Run-Time Scalable NoC for FPGA Based Virtualized IPs
Hiliwi Leake Kidane, El‐Bay Bourennane, Gilberto Ochoa‐Ruiz · 2017
The integration of virtualized FPGA-based hardware accelerators in a cloud computing is progressing from time to time. As the FPGA has limited resources, the dynamic partial reconfiguration capability of the FPGA is considered to share resources among different virtualized IPs during runtime. On the other hand, the NoC is a promising solution for communication among virtualized FPGA-based IPs. However, not all the virtualized regions of the FPGA will be active all the time. When there is no demand for virtualized IPs, the virtualized regions are loaded with blank bitstreams to save power. However, keeping active the idle components of the NoC connecting with the idle virtualized regions is not optimal for the total power consumption. In this paper, we have proposed a runtime scalable NoC where the NoC size is scaled up and down on demand. The experimental result shows that the total power consumption of the NoC can be reduced by more than 15% if the runtime scalable Noc is used.