A High-Performance and Area-Efficient VLSI Architecture for the PRESENT Lightweight Cipher
Jai Gopal Pandey, Tarun Goel, Abhijit Karmakar · 2018
Security and privacy are of prime concern in the emerging internet of things (IoT) and cyber-physical systems (CPS) based applications. Lightweight cryptography plays an essential role in securing the data in this emerging pervasive computing environments. In this paper, we propose a high-performance and area-efficient VLSI architecture with 64-bit datapath for the PRESENT block cipher. The proposed architecture performs an integrated encryption/decryption operation for both 80-bit and 128-bit key lengths. The architecture is synthesized for the Virtex-5 XC5VLX110T FPGA device, available on the Xilinx ML-505 platform. It has been observed that the proposed architecture utilizes 0.73% and 0.87% of FPGA slices for 80-bit and 128-bit key lengths, respectively. A throughput of 410 Mbps and power consumption is about 16 mW for both the key lengths.