Optimized area and speed architectures for the mix column operation of the advanced encryption standard
Sudhir Rao Rupanagudi, Varsha G. Bhat, Abhiram Srisai, M. Harshavardhan, S. Namitha, Sakinala Devi Naga Venkata Durgaprasad, Y Sree Harshitha, K. R. Kavya, Feba Chellappan, B. A. Harshitha, V. Vathsala, M. H. Surekha, G. N. Vachana, Vasanthi Satyananda · 2017
The advancements of The Internet has invoked a large increase in internet transactions and is also associated with a spurt in sharing of confidential, sensitive and private data over the World Wide Web. As a resultant of this, existing cryptographic methodologies such as the Advanced Encryption Standard (AES), which are at present protecting such data, are required to be swift and highly secure. This paper discusses two novel approaches for addressing the above issue and this has been made possible by optimizing the architecture of a vital step of the AES - the mix column operation. In terms of speed efficacy, an improvisation of 1.27 times was attained in comparison to previous algorithms. In terms of hardware architecture, an area optimization of around 3 times was also achieved. All speed and area calculations were performed for the Artix-7 series of FPGA by Xilinx.