Fixed latency serial transceiver with single bit error correction on FPGA
A. S. Aiswarya, Anu George · 2017 International Conference on Trends in Electronics and Informatics (ICEI) · 2017
Serial links are essential components for communication. High speed Serializer-Deserializer (SerDes) chips are typically designed for variable latency error correction associated with a set of data transferred at a time. Here, we propose a fixed latency serial transceiver with bit error correction. Fixed latency serial links operations requires dedicated circuitry and they are usually not needed for most communication operations. In this work, we present a link architecture based on the high speed SerDes with bit error correction embedded in Xilinx Spartan6 Field Programmable Gate Arrays (FPGAs).