Evaluation of NoC on multi-FPGA interconnection using GTX transceiver
Atef Dorai, Olivier Sentieys, Helene Dubois · 2017
Multi-FPGA platforms are very popular today for pre-silicon verification of complex designs due to their low cost and high speed. The idea is to divide these systems into smaller sub-systems and implement each one on a separate chip. The challenge is that the number of IOs available on FPGA remains constant despite the technological evolution. This problem is resolved by multiplexing several cut-signals using the time division multiplexing scheduling mechanism. This structure has a strong effect on the speed of transmission between FPGAs. However, an inter-FPGA bottleneck appears. In this paper, we focus on evaluating the Network-on-Chip on multi-FPGA using the high speed serial transceiver GTX block. In order to speed up the transmission between FPGAs, GTX Transceiver is used to provide a high bandwidth while using fewer pins connections. Depending on the available multi-gigabit transceiver, the bandwidth per connection can reach 12.5 Gb/s which allows for large amounts of data to be moved quickly between multiple FPGAs. In our evaluation, a VC707 platform based on the Virtex-7 device is used. The simulation results show that the proposed architecture provides low area consumption and latencies under different traffic patterns.