Design and Implementation of a Novel Bit-Parallel Systolic Multiplier Over GF(2m) for Irreducible Pentanomials
Sudha Ellison Mathe, Lakshmi Boppana · Journal of Circuits Systems and Computers · 2018
Cryptography in current digital world offers integrity and confidentiality of data being transferred over a communication network. Modern cryptography provides such security through cryptographic algorithms which mainly involve multiplication operation in finite fields. Since the finite field multiplication operation is a computationally intensive operation, various algorithms and architectures are proposed in the literature to obtain efficient finite field multiplications in both hardware and software. In this paper, a modified interleaved multiplication algorithm to perform multiplication of two finite field elements over GF(2m) for pentanomials is derived from a conventional interleaved multiplication algorithm using a novel Pre-Computation (PC) technique to reduce the computational complexity of the algorithm. Consequently, an m-bit systolic multiplier for pentanomials (SMP) is designed by employing the proposed algorithm. Hardware and delay complexity analysis is performed and comparison of the proposed SMP structure with similar multipliers available in the literature is presented. The SMP structure achieves about 28% improvement in hardware for [Formula: see text] when compared with the best multiplier available in the literature. The functionality of the proposed SMP structure is verified by implementing on a field-programmable gate array (FPGA) Virtex-7 (XC7V2000TFLG1925-2) prototype board and synthesizing in application specific integrated circuit (ASIC) using Synopsys Design Vision compiler with 90[Formula: see text]nm generic library. It can be observed from FPGA and ASIC implementation results that the proposed SMP structure shows improvement in area and power consumption when compared with similar multipliers available in the literature.