High-quality UHD demosaicing on low-cost FPGA
Pavel S. Baranov, Leonid I. Ivanov · 2018
In our time more and more digital camera developers are beginning to use UHD resolution. This way of design evolution allows us to greatly increase overall quality of captured image. With increasing of total pixel amount, we can implement new features without dramatic resolution loss, like digital zoom or geometric aberration correction. While resolution and quality grows, either does pipeline bandwidth of video processor. In 12G-SDI video stream, pixel clock is 596 MHz, which is defining while choosing FPGA, where our video processor will be implemented in. Intel and Xilinx recommends to use very high-cost FPGA, like: Arria, Stratix, Virtex and Kintex. In this paper, we will present an approach to design a pipeline that will process demosaicing of 4K 60 FPS video stream on low-cost FPGA Intel Cyclone V.